In general, a portable device adopting computer architecture employs an SRAM (Static Random Access Memory) exhibiting a high speed as a main storage part while a highly integrated nonvolatile flash memory is used as an auxiliary storage part. FIG. 21 is a block diagram showing the structure of a memory system in a conventional portable device having such a structure. In the prior art shown in FIG. 21, an SRAM 102 is employed as a main storage part storing data of a CPU (central processing unit) 103. A flash memory 101 is employed as an auxiliary storage part.
In the case of the conventional structure shown in FIG. 21, two chips of the flash memory 101 and the SRAM 102 are generally required, and hence this is disadvantageous to miniaturization of the device. This structure is also disadvantageous in speed since a delay is caused by wires between the chips.
In order to solve such inconvenience, a product prepared by pasting a chip of a flash memory 101 and a chip of an SRAM 102 together and storing the same in a single package has also been developed in recent years. FIG. 22 is a perspective view showing the structure of such a conventionally developed semiconductor package. In this semiconductor package, it is possible to deal with a certain degree of miniaturization by superposing the chip of the flash memory 101 and the chip of the SRAM 102 vertically, as shown in FIG. 22.
In the product shown in FIG. 22 prepared by superposing the chip of the flash memory 101 and the chip of the SRAM 102 vertically and storing the same in the single package, however, it has been difficult to reduce the thickness in the height direction due to the superposition of the two chips. Thus, there has been such a problem that it is difficult to attain further miniaturization (thinning).
Further, the chip of the flash memory 101 and the chip of the SRAM 102 are wired with wires 104 by solder or the like, and hence parasitic capacitances increase. Thus, there has also been such a problem that power consumption enlarges to inhibit speed-up.
With respect to requirement for reduction of the power supply voltage for the portable device, there has been such inconvenience that a high voltage is required for writing in memory cells of the flash memory 101. There has also been such inconvenience that the area and power consumption of a step-up circuit 101a for generating a high voltage enlarge. Therefore, it has been difficult to attain reduction of the power supply voltage and reduction of power consumption of the portable device.
A ferroelectric memory is known as one of recently remarked nonvolatile memories. This ferroelectric memory is a memory utilizing capacitance change responsive to the direction of polarization of a ferroelectric substance as a memory element. This ferroelectric memory, capable of data writing at a high speed and a low voltage in principle, is remarked as a nonvolatile memory of the next generation.
Among memory cell systems for the ferroelectric memory, a two-transistor two-capacitor system and a one-transistor one-capacitor system are lower in degree of integration as compared with the flash memory, and hence insufficient as substitutions for the flash memory. On the other hand, a simple matrix ferroelectric memory has a simple structure of merely arranging ferroelectric capacitors on the intersections between word lines and bit lines can be highly integrated. Therefore, the simple matrix ferroelectric memory is remarked as a substitutable memory for the flash memory.
However, the simple matrix ferroelectric memory has a problem of such disturbance that data in non-selected cells disappear. In other words, it follows that a voltage of ½Vcc is applied to non-selected memory cells connected to a selected bit line and a selected word line in writing and reading. Therefore, there is such a problem that the quantity of polarization gradually decreases due to hysteretic properties of the ferroelectric substance and the data disappear as a result.